Semiconductor technology pervades most electronic devices today. Computers, televisions, videocassette recorders, cameras, etc., all use semiconductor integrated circuits to varying degrees. For example, the typical computer includes microprocessors and dedicated controller integrated circuits (i.e., video controllers, audio controllers, etc.), as well as memory, such as dynamic random-access memory. The design of semiconductors, therefore, is a crucial consideration of the design of almost any electronic device.
One type of semiconductor design is the design of semiconductor test structures. A semiconductor integrated circuit, for example, must be able to operate in a variety of different conditions (varying temperatures, for example), and perform within a variety of different specifications (i.e., speed, power consumption, etc.). Semiconductor test structures are therefore utilized to ensure that various components of a given semiconductor will perform according to specification in different conditions. Test structures are not integrated circuits sold to end consumers as part of an electronic device, but rather are used internally to ascertain that the end products will perform correctly.
To aid in the design of semiconductors in general, and the design of semiconductor test structures in particular, software such as Design Framework II (DF2), available from Cadence Design Systems, Inc., has been developed. DF2, for example, includes an editor that permits a designer to place various components over a semiconductor substrate as necessary. DF2 also provides for a degree of flexibility in the design of such components. Specifically, DF2 includes parameterized cells, or pcells, that allow the designer to create customized instances of a pcell every time the pcell is placed on a layer. For example, a transistor can be created and have parameters assigned thereto to provide for control of its width, length, and number of gates. When instances of the transistor are placed on the layer, different values may be assigned to each of these parameters. According to the parameter values, each instance varies in size and composition.
The pcell approach of DF2, however, is a top-down semiconductor design approach, and thus has limitations and disadvantages associated with it. A designer may, for example, first draw a transistor, and then program that transistor to respond to parameters that will cause various parts of the design to take on those parameter values. This can be a very complex, tedious and error-prone process. For example, if the designer desires contacts to fill in the available active area space while maintaining a certain pitch and minimum separation from the active area edge, the equations to accomplish this for an arbitrarily sized active area are complex within DF2. Furthermore, these equations are specific to the transistor under development. If the designer desires to design another parameterized object—for example, a field transistor or a contact chain—he or she needs to repeat the entire process.
A solution to the limited flexibility of pcells within DF2 is described in the co-pending, co-filed and co-assigned patent application entitled “Hierarchical Semiconductor Structure Design.” In this application, a hierarchy of abstractions of a semiconductor structure is described. At the lowest level are basic atom cells, which are combinable into higher-level cells, which are combinable into devices, which are finally combinable into a test structure. In this manner, changing the parameters of a structure automatically changes the parameters of the constituent devices, higher-level cells, and basic atom cells. That is, changing the parameters of a structure does not require redesign of the structure. Thus, this application describes a hierarchical design approach that affords designers much greater flexibility and efficiency.
However, where semiconductor structure designers instill their rules for test structures in a separate document or file, they still must translate these rules by hand into parameters for the structures (and potentially in other cells that may be used in a hierarchical semiconductor structure design). This renders the hierarchical semiconductor structure design approach potentially vulnerable to mistakes in keying in the parameters, and also adds a potentially time-consuming and labor-intensive step in changing the parameters of a structure based on new design rules. Furthermore, if the semiconductor designer wishes to ensure that all contacts in the many instances of cells that he or she may have placed all have exactly the same contact size, for example, the designer will have to visit each cell and check that the values are the same in each. There is no facility for creating a global input parameter that ensures a universal value for a specific parameter in each cell instance.
There is a need, therefore, for a more efficient and less error-prone manner by which design rules are translated into parameters for structures and other cells, and the parameters keyed into these structures and other cells. Such a manner should allow for the inputting of global parameters to ensure that universal values for a specific parameter in each of a plurality of cell instances are entered, as well.